1. Field of the Invention
The invention relates generally to plasma-enhanced processing of semiconductor wafers and, more specifically, to an apparatus for improving voltage stability on a workpiece and electrical coupling between a plasma and the workpiece in a semiconductor wafer processing system.
2. Description of the Background Art
Plasma-enhanced reactions and processes have become increasingly important to the semiconductor industry, providing for precisely controlled thin-film depositions. For example, a plasma reactor in a high-temperature physical vapor deposition (PVD) semiconductor wafer processing system generally comprises a reaction chamber for containing a reactant gas, a pair of spaced-apart electrodes (cathode and anode) that are driven by a high power DC voltage to generate an electric field within the chamber, and a substrate support for supporting a substrate within the chamber. The cathode is typically a target material that is to be sputtered or deposited onto the substrate, while the anode is typically a grounded chamber component. The electric field, creating a reaction zone, capture electrons thereby ionizing the reactant gas into a plasma. The plasma, characterized by a visible glow, is a mixture of positive and negative reactant gas ions and electrons. Ions from the plasma bombard the negatively biased target releasing electrically neutral deposition material. As such, a conductive deposition film forms on the substrate which is supported and retained upon the surface of the pedestal. Additionally, a deposition ring assembly circumscribes the pedestal. This ring assembly contains a number of concentric rings that assist with wafer process functions. For example, a shadow ring and cover ring prevent deposition material from being deposited on surfaces other than the substrate.
To further enhance deposition in an ion metallization system, a specific type of PVD system, the substrate and pedestal are biased negatively with respect to the plasma. This is accomplished by providing RF power to the pedestal. A negative DC offset accumulates on the pedestal as a result of the higher velocity of electrons as compared to the positive ions in the plasma. In some processes, as neutral target material is sputtered off the target and enters the plasma, the target material becomes positively ionized. With the negative DC offset at the pedestal, the positively ionized target material is attracted to and deposits on the substrate more readily than on an unbiased pedestal. Ordinarily, a 400 KHz AC source is used to bias the pedestal, but other frequency sources such as a 13.56 MHz source may also be used.
Ideally, the voltage magnitude at the substrate (i.e., a semiconductor wafer) remains stable during processing and is reproducible from wafer-to-wafer over an entire processing cycle. That is, the voltage level at the wafer remains constant as the target material is being deposited onto the wafer. A stable voltage level at the wafer causes the ionized deposition material to be drawn uniformly to the wafer. A uniform deposition film layer is a highly desirable characteristic in the semiconductor wafer manufacturing industry. Additionally, the same stable voltage magnitude must reproduce or occur as each new wafer is processed. Reproducing the same stable voltage magnitude for each new wafer is also desirable as it reduces the amount of improperly processed wafers and improves the accuracy of the film deposition amongst a batch of wafers. As such, overall quality of manufactured product increases.
The characteristics of voltage stability and reproducibility are optimized when the wafer is the only electrical conductor in direct contact with the plasma. That is, voltage stability and reproducibility is maintained when the wafer forms the path of least resistance for power coupling. Existing pedestal configurations allow for various electrical paths wherein voltage stability is compromised. One such electrical path establishes through one of the aforementioned rings in the process chamber. The rings are made of conductive material (e.g., stainless steel) which have instantaneous impedance values that are lower than the impedance of the pedestal/wafer combination. As such, the high voltage conducts to the plasma through one or more of the rings in lieu of, or in addition to, a path through the wafer. When a ring becomes the momentary path of least resistance, voltage instability occurs at the wafer. The resultant instability of the wafer voltage causes the aforementioned nonuniformity of film deposition on the wafer.
Voltage stability is also compromised when the DC bias level on the wafer is different from that of another local conductor (i.e., a deposition ring assembly). When the potential difference between two conductors in the process chamber becomes too large, arcing can occur. Arcing is deleterious because a large enough discharge creates particles in the chamber that may be deposited on the wafer. Arcing is undesirable because it also creates another temporary conductive path that shifts the plasma away from the wafer and damages the wafer surface.
Consequently, there is a need to electrically isolate the conductive path from the pedestal to the plasma, via the wafer. Electrical isolation stabilizes wafer voltage thereby improving the deposition process.
Therefore, there is a need in the art for an apparatus that optimally conducts power from a pedestal through the wafer and plasma to optimize wafer voltage stability and reproducibility.